1. Field of the Invention
This invention relates to vertical type junction field effect transistors.
2. Description of the Prior Art
Recently the development of vertical type junction field effect transistors (hereinafter referred to by the abbreviation FET) having triode characteristics has occurred, and attention has been particularly directed to them by the fact that they can be used as elements for controlling relatively large quantities of electric power. FIG. 1 shows the structure of a known multi-channel vertical type FET which is useful in integrated circuits. The body 1 of the device consists for example of an N- type region with an N+ type layer beneath it. In the top surface of the N- region, a plurality of P+ type gate regions 3 are formed as an interconnected mesh and a shallow source region 4 of N+ conductivity type is formed so as to overlie most of the gate regions. A plurality of channel regions are present in the high resistance N- region and are positioned between the various gate regions 3 whereby current flowing through the channel regions between the drain and source of the device is controlled. D is a drain terminal which is connected to drain electrode 5 provided for example by vacuum evaporation of aluminum or the like on the bottom surface of the body 1. G and S are, respectively, a gate terminal and a source terminal which are connected respectively to a gate electrode 6 and a source electrode 7 which are similarly provided.
A vertical type FET having the structure described above is designed so as to make use, to the extent possible, of the advantages of the bipolar type of element and of the electric field effect transistor, and in the same vertical type FET there is an epitaxial structure in which gate regions are embedded in the interior of the body of the device by the gas phase growth method. By the method described hereinafter, the above mentioned vertical type FET has a double diffusion structure whereby the process of its manufacture is very greatly simplified.
More specifically the body 1 of the device consisting of the N- type region and the N+ type layer, which subsequently becomes the drain region, is formed and an oxide film is provided on the top surface of the N- type region and on top of this film a film of photo resist is provided. This photo resist film is selectively etched and holes are formed in the oxide film in order to form the gate regions. A mask in the form of a round or square mesh is used, and the mesh covers the parts where the source regions are to be formed. The width of the mesh forming the gate regions is about 5 microns, and boron, for example, is diffused as a P type impurity into the N- type region. After these P type gate regions have been formed, the gate regions are covered with an oxide film. Then, a large window overlying approximately the whole of the gate regions is formed in the oxide film. Through this window an N type impurity, for instance, phosphorus or the like, is shallowly diffused in a high concentration so that an N+ type source region 4 is formed so as to substantially cover the gate regions 3 as shown in FIG. 1.
The PN junction surfaces are not exposed at the surface of the body of the device and the junction capacitance is smaller than in previously known FETs, besides which the resistance to voltage is improved. This is because the gate and source regions are formed by N- P+ junctions, the current between the drain and source exhibits triode characteristics and the characteristic of the saturation current flowing through the channel regions is improved.
FIG. 2 illustrates the states of a depletion layer in a channel region to show the principle of operation of this vertical type FET. FIG. 2a shows the state of the depletion layer in the vicinity of the gate junctions when there is no gate bias voltage V.sub.G. This depletion layer when bias is not applied is produced by the internal electric field which is present at the PN junction between gate and source.
If a voltage V.sub.D is applied between the source and drain, a drain current I.sub.D flows readily in the channel region and the V.sub.D I.sub.D characteristics of the device is shown in FIG. 3. However, if a gate voltage V.sub.G is applied then, as shown in FIG. 2b, the depletion layer extending outwardly from the gate regions narrows the width of the channel which is between the gate regions and the drain current I.sub.D flows less readily and the V.sub.D - I.sub.D characteristic varies as shown in FIG. 3 and in a form in which the channel resistance becomes greater. If an even greater negative gate voltage V.sub.G is applied, then, as shown in FIG. 2c, the depletion layer from the gate regions "pinches off" the channel region. Thus, even though the drain voltage V.sub.D is applied, the channel is blocked by the depletion layer and the drain current I.sub.D does not flow. Of course, if an additional drain voltage V.sub.D is applied, breakdown of the depletion layer occurs and current can be made to flow. FIG. 2d shows the state of the depletion layer immediately before the breakdown; the drain voltage V.sub.D causing transformation to occur on the drain region side. Thus, as shown in FIG. 3, as the gate voltage V.sub.G becomes increasingly negative, the drain voltage V.sub.D necessary for commencement of the flow of the drain current I.sub.D becomes greater and it becomes possible to approximately obtain the characteristics of a triode.
Again considering a vertical type FET having these characteristics, with reference to the embodiment shown in FIG. 1, it is found that the spacing of the gate regions 3, that is to say the width of the channel regions, is determined by the diffusion of an N+ layer as the source region 4 under the source electrode 7. The gate regions 3, accordingly, are mutually continuous in mesh form in a plane. However, above the gate regions where a gate electrode 6 is not provided, the gate regions 3 are prevented by the above mentioned N+ layer from being exposed to the surface of the main body 1 of the device. Therefore, in the vicinity of the surface, the gate regions are in a form in which they are cut off by the second diffusion of the N+ layer. Accordingly, the gate series resistance r.sub.G becomes large, the extension of the depletion layers in the channel regions does not readily pinch off the channels, the junction plane of the gate regions 3 and the source region 4 is so formed as to extend over the whole top surface of the gate regions 3 and the junction capacity C.sub.GS becomes large. Therefore, the time constant C.sub.GS . r.sub.G on the gate input side becomes large and during high frequency operation the drain current I.sub.D cannot be controlled.